Start VLSI career with 100% placement assistance.

Designed & Delivered by Industry Experts.

We offer industry standard, high quality, affordable training to students who wish to pursue a career in VLSI .

Arist automation has introduced an end to end VLSI Course for fresh graduates and industry professionals.

The VLSI design course is designed to meet the ever growing demand of the electronic industry. Our VLSI training course is the right combination of classroom sessions, hands-on experience and live real time projects. The training consists of classroom lectures and practical sessions in the initial training program, which is later followed by industry projects in the next training program. After successfully completing the VLSI training program students become proficient and job ready in diverse areas of VLSI Logic and Physical design. The VLSI training program is designed in such a way that candidates master the concepts and design requirements.

This VLSI course is about basic concepts of VLSI System Design. This course will cover end-to-end concepts from basic Elemental Physics, Device Physics to Chip Design like – ASIC, FPGA design flows, and trains engineers extensively on the VLSI design methodologies viz CMOS, VHDL, Verilog and System Verilog. 

VLSI Course Modules:

Module 1 -Linux
 Introduction : OS
 Introduction : Linux OS
 Basic Linux, commands
 Managing Disk files and directories (folders)
 Managing documents – inputs and outputs
 Text Editors – vim
 Shell Programming – scripting in linux
 Labs, Exercises
 Advance Linux: Advanced commands, functions
 Labs, Exercises, Exam

Module 2-Perl
 Introduction
 Data Types- Numbers, Strings, Variables, Operators & Precedence
 Control Statements, Data Structures (Lists, Arrays, Hash)
 Writing PERL scripts, Cheat Sheet
 Labs, Exercises, Exam, Project
• Advanced Data Structures, Process Management
• Errors & Exceptions (interrupts) handling, Sockets (IPC)
• External Interface Examples:- CGI Interface, Net (HTML), Interface,
• Database (MySQL) Interface, C Interface.

Module 3-Digital Design
 Basics of Digital Design
 Understanding Combinational Logic/Circuit Designing
 Canonical forms – SOP, POS
 Understanding Sequential Logic/Circuit Designing
 Digital Design Flow Modeling
• Language Specification
• VHDL/Verilog digital model example
 Computer Architecture – RISC, CISC
 Advanced Digital Design
 Exercises, Exam

Module 4-Verilog
 Introduction
 Gate level modeling, modeling and concept of wire
 creation, module instantiation, ports and their mapping,
 Dataflow modeling, Various Operators
 Verilog Language & data types
 Modeling Delays – specparam
 Behavioral modeling
 Modeling circuits using all the three modeling styles
 Behavioral modeling, File I/O
 Switch Level Modeling, User Defined Primitives
 Modeling Design Examples (ALU, ROM, RAM, FSM, TRAFFIC LIGHT, CLOCK, USING COUNTER, UART)

Module 5-FPGA
 Introduction to FPGA (Architecture :CPLD, FPGA,FPGA working, References)
 design flow, design tricks
 H/W components on FPGA board and their working
 Xilinx ISE tool installation and working
 Designing basic FPGA examples (Adder, Subtractor, Counter etc.)
 Designing advanced FPGA examples (Key Board Interfacing, VGA,
 Monitor interfacing, UART, burn these models on available FPGA kit

Module 6- C & Data Structure
 Introduction to C language
 Basic Building Blocks of C
 Control Flow
 Modular Programming
 C Preprocessor directives:- Macro definitions, Header file(s) and their inclusion, Conditional compilation
 Input / Output:- print formats, Standard I/O, File I/O, C standard libraries & related functions
 Advanced Data Types:- Pointers & Arrays, Strings & Enumerations,
 Structures & Unions, User defined data types – typedef
 Data Structures Creation (Arrays, linked lists, Stacks, queues & priority queues, hash tables

Module 7- System Verilog
 Introduction about Verification
 Data Types & Operators
 Procedural Statements
 Tasks & functions
 Hierarchy & Connectivity
 Various Interfaces
 Object Oriented Paradigm (OOPS
 Program & Clocking Block
 Inter Process Communication (IPC):- events, semaphores, mailboxes
 Randomization:- Class based randomization, Constraints
 System Verilog Assertions:-properties & sequences, assert, assume, cover directives
 Functional Coverage
 TLM (Transaction Level Modeling) & UVM

Module 8 – CMOS
 Project Work

Module 9-
Soft Skill Training